1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices, more particularly to a process for integration of a trench for the capacitor in Dynamic random access memories (DRAMs) and removal of black silicon.
2. Description of the Related Art
DRAM designs have been proposed which incorporate capacitors having vertical extensions below the surface of the silicon wafer (cylinder trench capacitors or bottle shaped trench capacitors). The trench for capacitors is formed by selectively etching the silicon wafer (semiconductor substrate). In the trench-etching step, so-called black silicon tends to be formed on the exposed silicon wafer at the edge or peripheral portion. The black silicon may be a silicon spike having a length of about 4 to 6 micrometers.
During subsequent processes, this black silicon can be broken off to form particles that become a cause of electrical insulation defects, having an adverse affect on manufacturing yield of DRAMs.
Therefore, improved methods to remove the black silicon during formation of the trench for capacitors are needed.
FIGS. 1A to 1F are cross-sections showing the manufacturing steps of a trench for capacitors in a semiconductor substrate, in accordance with the conventional skill.
FIG. 1A shows a semiconductor (silicon) substrate 10 having a memory cell region I and an edge region II. A hard mask HM consisting of pad oxide 12, silicon nitride 14, and boro-silicate glass layer 16 is formed on the semiconductor substrate 10. Next, the hard mask HM is used as the etching mask to etch the semiconductor substrate 10 to create a capacitor trench 18 by anisotropic reactive ion etching (RIE). In the step, black silicon spikes 22 are generated on the semiconductor substrate 10 at the edge region II without protection of the hard mask HM.
Next, as shown in FIG. 1B, a first photoresist material PR1 is covered on the semiconductor substrate 10 at the memory cell region I while exposing the upper surface of the semiconductor substrate 100 at the edge region II. As shown in FIG. 1C, the black silicon spikes 22 are then isotropically etched while the photoresist material PR1 is used as the etching mask to obtain a semiconductor substrate 10 having a rounded surface ES at the edge region II. The photoresist material PR1 is stripped and cleaned to expose the capacitor trench 18. A thermal oxide film 20 is formed on the capacitor trench 18 by thermal oxidation.
Referring now to FIG. 1D, a second photoresist material PR2 is spin coated on the semiconductor substrate 10 at the memory cell region I to fill the capacitor trench 18 having the thermal oxide film 20.
Next, as shown in FIG. 1E, the second photoresist material PR2 is partially etched to leave photoresist material PR2xe2x80x2 at the bottom portion of the capacitor trench 18 and expose the thermal oxide film 20. The exposed thermal oxide film 20 is removed to leave thermal oxide film 20a at the bottom portion of the capacitor trench 18.
Afterward, referring to FIG. 1F, the photoresist material PR2 is stripped to expose the thermal oxide film 20a. 
However, the conventional method of forming a trench for capacitors described above entails high processing complexity and costs (formation/removal of photoresist material PR1 and photoresist material PR2).
In view of the above disadvantages, an object of the invention is to provide a process for integration of a trench for capacitors and removal of black silicon without formation/removal of photoresist PR1 and photoresist PR2. Therefore, the process complexity and manufacturing cost can be reduced.
In accordance with one aspect of the invention, there is provided a process for integration of a trench for capacitors and removal of black silicon, suitable for a semiconductor substrate having a memory cell region and an edge region. First, an etching mask is formed on the semiconductor substrate. The semiconductor substrate is etched to form a capacitor trench having a predetermined depth while the etching mask is used as the shield, and black silicon spikes are generated on the semiconductor substrate at the edge region. A thermal oxide film is conformally grown on the capacitor trench. A sacrificial layer is then formed on the upper surface of the semiconductor substrate at the memory cell region, wherein the sacrificial layer is filled into the capacitor trench. The black silicon spikes are removed while the sacrificial layer is used as the shield. The sacrificial layer is partially removed to expose the thermal oxide film formed in the top portion of the capacitor trench and leave a sacrificial structure at the bottom portion of the capacitor trench. The exposed thermal oxide film is then removed. Finally, the residual sacrificial structure is removed.
In accordance with another aspect of the invention, there is provided a process for integration of a trench for capacitors and removal of black silicon. The formation of the etching mask further comprises the steps of:
growing a pad oxide on the semiconductor substrate;
depositing a silicon nitride on the pad oxide;
forming a silicon oxide layer/or boro-silicate glass on the silicon nitride;
selectively etching the silicon oxide layer/or boro-silicate glass, silicon nitride, and the pad oxide to create the stacked etching mask.
In accordance with further aspect of the invention, there is provided a process for integration of a trench for capacitors and removal of black silicon. The thermal oxide film in step (c) can be formed by thermal oxidation in an ambient containing oxygen or by chemical vapor deposition at an elevated temperature.
In accordance with yet another aspect of the invention, there is provided a process for integration of a trench for capacitors and removal of black silicon. The sacrificial layer preferably consists of an organic material or a photoresist material.
In accordance with a still further aspect of the invention, there is provided a method process for integration of a trench for capacitors and removal of black silicon. The formation of the capacitor trench in step (b) is preferably performed by ion reactive etching. Furthermore, the black silicon spikes are preferably removed by isotropic etching. Also, removal of the black silicon spikes and the sacrificial layer in steps (e) and (f) can be performed by the same etching tool.